module top(
           input clk,
           input rst_n,
           input new_cntr_preset,
           output out
       );

wire [3: 0] lfsr_cnt_xor;
reg [3: 0] lfsr_cnt, lfsr_cnt_nxt;
assign lfsr_cnt_xor[0] = lfsr_cnt[1];
assign lfsr_cnt_xor[1] = lfsr_cnt[2];
assign lfsr_cnt_xor[2] = lfsr_cnt[3] ^ lfsr_cnt[0];
assign lfsr_cnt_xor[3] = lfsr_cnt[0];


always@( * )
	begin
		if (new_cntr_preset)
			lfsr_cnt_nxt = 4'b1111;
		else
			lfsr_cnt_nxt = lfsr_cnt_xor;
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			lfsr_cnt <= 4'b1111;
		else
			lfsr_cnt <= lfsr_cnt_nxt;
	end

assign out = (lfsr_cnt == 4'b1111);
endmodule
